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INTEGRATED CIRCUITS
DATA SHEET
74AVC16374 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Product Specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC24 2000 Mar 09
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
FEATURES * Wide supply voltage range from 1.2 to 3.6 V * Complies with JEDEC standard no. 8-1A/5/7 * CMOS low power consumption * Input/output tolerant up to 3.6 V * DCO (Dynamic Controlled Output) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation * Low inductance multiple VCC and GND pins to minimize noise and ground bounce * Supports Live Insertion. DESCRIPTION
74AVC16374
The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The 74AVC16374 consist of 2 sections of eight edge triggered flip-flops. A clock input (CP) and an output enable (OE) are provided per 8-bit section. The 74AVC16374 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, nOE should be tied to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figs 1 and 2).
MNA506
handbook, halfpage
0
MNA507
handbook, halfpage
300
I OH (mA) 1.8 V -100
I OL (mA) 200 2.5 V 2.5 V
3.3 V
-200
100
1.8 V
3.3 V -300 0 0 1 2 3 VOH (V) 4 0 1 2 3 VOL (V) 4
Fig.1
Output voltage as a function of the HIGH-level output current.
Fig.2
Output voltage as a function of the LOW-level output current.
2000 Mar 09
2
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.0 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQn CONDITIONS VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V fmax maximum clock pulse frequency VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CI CPD input capacitance power dissipation capacitance per buffer notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUTS OPERATING MODES nOE Load and read register Load register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high impedance OFF-state; = LOW-to-HIGH CP transition. 2000 Mar 09 3 L L H H nCP nDn l h l h INTERNAL FLIP-FLOPS L H L H 66 1 3.1 2.4 2.0 1.5 1.3 250 300 320 350 350 5.0
74AVC16374
TYP. ns ns ns ns ns
UNIT
MHz MHz MHz MHz MHz pF pF pF
OUTPUTS nQn L H Z Z
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
ORDERING AND PACKAGE INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74AVC16374DGG PINNING PIN 1 2, 3, 5, 6, 8, 9, 11 and 12 4, 10, 15, 21, 28, 34, 39 and 45 7, 18, 31 and 42 13, 14, 16, 17, 19, 20, 22 and 23 24 25 26, 27, 29, 30, 32, 33, 35 and 36 37, 38, 40, 41, 43, 44, 46 and 47 48 1OE 1Q0 to 1Q7 GND VCC 2Q0 to 2Q7 2OE 2CP 2D7 to 2D0 1D7 to 1D0 1CP SYMBOL DESCRIPTION output enable input (active LOW) 3-state flip-flop outputs ground (0 V) DC supply voltage 3-state flip-flop outputs output enable input (active LOW) clock input data inputs data inputs clock input -40 to +85 C PINS 48 PACKAGE TSSOP
74AVC16374
MATERIAL plastic
CODE SOT362-1
2000 Mar 09
4
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
74AVC16374
handbook, halfpage
1OE 1 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 2 3 4 5 6 7 8 9
48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 47 46 44 43 41 40 38
handbook, halfpage
1 1OE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1CP 48
24 2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2CP 25
MNA576
2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
MNA575
16374
36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
37 36 35 33 32 30 29 27 26
Fig.3 Pin configuration.
Fig.4 Logic symbol.
2000 Mar 09
5
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
74AVC16374
handbook, halfpage
1OE 1CP
1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN C1 2EN C2 1D 1 2 3 5 6 8 9 11 12 2D 2 13 14 16 17 19 20 22 23
MNA577
2OE 2CP 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
1D0 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2OE 2CP 2D0 1CP 1OE
D CP
Q
1Q0
FF1
to 7 other channels
D CP
Q
2Q0
FF9
to 7 other channels
MNA578
Fig.5 IEEE/IEC logic symbol.
Fig.6 Logic diagram.
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6
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage CONDITIONS according to JEDEC Low Voltage Standards MIN. 1.4 1.65 2.3 3.0 for low-voltage applications VI VO Tamb tr, tf DC input voltage DC output voltage output 3-state output HIGH or LOW state operating ambient temperature in free air input rise and fall time ratios VCC = 1.4 to 1.6 V VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V 1.2 0 0 0 -40 0 0 0 0
74AVC16374
MAX. 1.6 1.95 2.7 3.6 3.6 3.6 3.6 VCC +85 40 30 20 10 V V V V V V V V
UNIT
C ns/V ns/V ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60 C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage DC input diode current DC input voltage DC output clamping diode current DC output voltage DC output sink current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +85 C; note 2 VI < 0 for inputs; note 1 VO < 0 output HIGH or LOW state; note 1 output 3-state; note 1 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +4.6 -50 +4.6 -50 V mA V mA UNIT
VCC + 0.5 V +4.6 50 100 +150 500 V mA mA C mW
2000 Mar 09
7
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL VIH PARAMETER OTHER HIGH-level input voltage VCC (V) 1.2 1.4 to 1.6 2.3 to 2.7 3.0 to 3.6 VIL LOW-level input voltage 1.2 1.4 to 1.6 2.3 to 2.7 3.0 to 3.6 VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -3 mA IO = -4 mA IO = -8 mA IO = -12 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 3 mA IO = 4 mA IO = 8 mA IO = 12 mA II Ioff IIHZ/IILZ IOZ ICC input leakage current per pin power-off leakage current input current for common I/O pins 3-state output OFF-state current quiescent supply current VI = VCC or GND VI or VO = 3.6 V VI = VCC or GND VI = VIH or VIL; VO = VCC or GND VI = VCC or GND; IO = 0 1.65 to 3.6 1.4 1.65 2.3 3.0 1.4 to 3.6 0 1.4 to 3.6 1.4 to 2.7 3.0 to 3.6 1.4 to 2.7 3.0 to 3.6 - - - - - - - - - - - - GND 0.10 0.10 0.26 0.36 0.1 0.1 0.1 0.1 0.1 0.1 0.2 1.65 to 3.6 1.4 1.65 2.3 3.0 VCC - 0.20 VCC - 0.35 VCC - 0.45 VCC - 0.55 VCC - 0.70 VCC VCC - 0.23 VCC - 0.25 VCC - 0.38 VCC - 0.48 MIN. VCC 0.65 x VCC 1.7 2.0 - - - - - 0.9 0.9 1.2 1.5 - 0.9 0.9 1.2 1.5
74AVC16374
Tamb = -40 to +85 C TYP.(1) - - - - - GND 0.35 x VCC 0.35 x VCC 0.7 0.8 - - - - - 0.20 0.35 0.45 0.55 0.70 2.5 10 12.5 5 10 20 40 MAX.
UNIT V V V V V V V V V V V V V V V V V V V V A A A A A A A
1.65 to 1.95 0.65 x VCC
1.65 to 1.95 -
Note 1. All typical values are measured at Tamb = 25 C.
2000 Mar 09
8
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
AC CHARACTERISTICS GND = 0 V; tr = tf 2.0 ns. TEST CONDITIONS SYMBOL tPHL/tPLH PARAMETER WAVEFORMS propagation delay nCP to nQn see Figs 7 and 10 VCC (V) 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time nOE to nQn see Figs 8 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time nOE to nQn see Figs 8 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 tW nCP pulse width HIGH see Figs 7 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 tsu set-up time nDn to nCP see Figs 9 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 th hold time nDn to nCP see Figs 9 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 fmax maximum clock pulse frequency see Figs 7 and 10 1.2 1.40 to 1.60 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 Note - 1.2 1.0 0.8 0.7 - 1.6 2.3 0.9 0.7 - 2.5 1.8 1.0 1.2 - - 3.1 2.5 2.5 - 2.7 1.9 1.4 1.4 - 1.3 1.2 1.1 1.1 - - 160 200 200
74AVC16374
Tamb = -40 to +85 C MIN. TYP.(1) 3.1 2.4 2.0 1.5 1.3 5.4 3.9 3.3 2.3 2.0 5.6 4.5 3.3 1.8 2.0 0.8 0.5 0.3 0.2 0.2 -0.6 -0.3 -0.3 -0.2 -0.1 0.8 0.7 0.6 0.5 0.4 250 300 320 350 350 MAX. - 8.4 6.7 4.1 3.3 - 8.5 6.7 4.3 3.4 - 9.4 7.8 4.2 3.9 - - - - - - - - - - - - - - - - - - - -
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz
1. All typical values are measured at Tamb = 25 C and at VCC respectively 1.2, 1.5, 1.8, 2.5 and 3.3 V.
2000 Mar 09
9
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
AC WAVEFORMS
74AVC16374
handbook, full pagewidth
1/fmax VI nCP input GND tW t PHL VOH nQn output VOL VM
MNA579
VM
VM
t PLH
VCC 3.0 to 3.6 V
VM 0.5 x VCC
VI VCC VCC
2.3 to 2.7 V 0.5 x VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Clock input (nCP) to output (nQn) propagation delays.
handbook, full pagewidth
VI nOE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX t PZH t PZL VM
outputs disabled
outputs enabled
MNA478
VCC 2.3 to 2.7 V 3.0 to 3.6 V
VM 0.5 x VCC 0.5 x VCC
VX VOL + 0.15 V VOL + 0.3 V
VY VOH - 0.15 V VOH - 0.3 V
VI VCC VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.8 3-state enable and disable times.
2000 Mar 09
10
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
VI nCP input GND t su th VI nDn input GND VM t su th VM
74AVC16374
handbook, full pagewidth
VOH nQn output VOL The shaded areas indicate when the input is permitted to change for predictable output performance. VM
MNA580
VCC 2.3 to 2.7 V 3.0 to 3.6 V
VM 0.5 x VCC 0.5 x VCC
VI VCC VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.9 Data set-up and hold times for nDn input to nCP input.
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL R load VO R load
2 x VCC open GND
MNA505
VCC (V) 1.2 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 open 2 x VCC GND 1.4 - 1.6 1.65 - 1.95 2.3 - 2.7 3.0 - 3.6
VI VCC VCC VCC VCC VCC
Rload
CL
2000 15 pF 2000 15 pF 1000 30 pF 500 500 30 pF 30 pF
Fig.10 Load circuitry for switching times.
2000 Mar 09
11
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
PACKAGE OUTLINE TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
74AVC16374
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-10 99-12-27
2000 Mar 09
12
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74AVC16374
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 Mar 09
13
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods
74AVC16374
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 Mar 09
14
Philips Semiconductors
Product Specification
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
NOTES
74AVC16374
2000 Mar 09
15
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/02/pp16
Date of release: 2000
Mar 09
Document order number:
9397 750 06898

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